Floating body cell (FBC) memory (also known as zero-capacitor random access memory or Z-RAM™) offers a compromise between the speeds achieved by static random access memory (SRAM) and the densities achieved by dynamic random access memory (DRAM). FBCs typically implement one or more transistors implemented on a silicon on insulator (SOI) substrate. By making use of the floating body effect caused by the transistor operating on the SOI substrate, the transistor can be configured to store a charge similar to a capacitor, whereby the amount of charge stored at the transistor then can be sensed to determine the bit value stored by the transistor.
Due to its physical characteristics, a FBC typically is incapable of sourcing a relatively large current. Sense amplifiers used to sense the stored values of FBC memory cells thus are configured to be sensitive to relatively small differences in the output of the FBC. However, conventional sense amplifiers for FBC memories typically have delayed response times and are intolerant of transistor mismatch within the sensing circuitry. Accordingly, an improved technique for sensing stored bit values in a FBC memory would be advantageous.
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